

`define Inst_ROM_22X1024_SPROM_DATA_WIDTH    22
`define Inst_ROM_22X1024_SPROM_ADDR_WIDTH    10
`timescale 1ns/1ps
module Inst_ROM_22X1024_SPROM(
    input clka, 
    input ena,
    input [`Inst_ROM_22X1024_SPROM_ADDR_WIDTH-1:0] addra,
    output  [`Inst_ROM_22X1024_SPROM_DATA_WIDTH-1:0]douta
);


// ROM 1
wire CENY; // output dummy
wire [`Inst_ROM_22X1024_SPROM_ADDR_WIDTH-1:0] AY; // output dummy
wire [`Inst_ROM_22X1024_SPROM_DATA_WIDTH-1:0] Q;
wire  CLK;
wire  CEN;
wire [`Inst_ROM_22X1024_SPROM_ADDR_WIDTH-1:0] A;
wire [2:0] EMA;
wire  TEN;
wire  BEN;
wire  TCEN;
wire [`Inst_ROM_22X1024_SPROM_ADDR_WIDTH-1:0] TA;
wire [`Inst_ROM_22X1024_SPROM_DATA_WIDTH-1:0] TQ;
wire  PGEN;
wire  KEN; // 14


// ROM 1
assign douta = Q;
assign CLK = clka;
assign CEN = 1'b0;
assign #1 A = addra;
assign EMA = 3'b010;
assign TEN = 1'b1;
assign BEN = 1'b1;
assign TCEN = 1'b1;
assign PGEN = 1'b0;
assign KEN = 1'b1; // 10

// tie useless input IO to fixed state
assign TA = `Inst_ROM_22X1024_SPROM_ADDR_WIDTH'd0;
assign TQ = `Inst_ROM_22X1024_SPROM_DATA_WIDTH'd0; // 2



// Constant_rom256 (CENY, AY, Q, CLK, CEN, A, EMA, TEN, BEN, TCEN, TA, TQ, PGEN, // 13
//     KEN); // 1

// module rom_22_1024 (CENY, AY, Q, CLK, CEN, A, EMA, TEN, BEN, TCEN, TA, TQ, PGEN, KEN);


rom_22_1024 rom_22_1024_u0 ( .CENY(CENY), .AY(AY), .Q(Q), .CLK(CLK), .CEN(CEN), .A(A), .EMA(EMA),  // 7
                            .TEN(TEN), .BEN(BEN), .TCEN(TCEN), .TA(TA), .TQ(TQ), .PGEN(PGEN), .KEN(KEN)); // 7


endmodule